VHDL processor

Introduction

This project consists of the design and implementation of a custom processor in VHDL. The system uses a 32-bit instruction format that supports logical, arithmetic, data transfer, and conditional branch operations.

System Architecture

The processor follows an architecture that combines RISC principles with specialized instructions. Its modular design includes an ALU, Control Unit, UART, Program Counter, and a PortIO interface.

The ALU implements logical operations (AND, OR, and XOR), arithmetic operations, bit rotations, and saturating arithmetic, automatically limiting results to the maximum and minimum representable values to prevent overflow.

The Control Unit was one of the most challenging parts of the project. In the initial version, the finite state machine introduced an extra clock cycle of latency between instructions. While this was not an issue for isolated operations, consecutive instructions caused the processor to fall behind. After several iterations, I simplified the state machine and eliminated the unnecessary latency, allowing the processor to execute instructions continuously.

Testbench

Verification was carried out using a comprehensive testbench that exercises all processor features in different orders and combinations, trying to catch edge cases.

After simulation, the synthesized design achieved a Worst Negative Slack (WNS) of 0.932 ns with a 12 ns clock period, supporting operating frequencies above 80 MHz.

Key Takeaways

This project reinforced the importance of maintaining a modular architecture. Dividing the design into independent blocks made it much easier to test each component individually and fix issues without affecting the rest of the processor.

I also learned that rethinking an implementation is often more effective than continuing to add new features. Simplifying the Control Unit state machine and reorganizing the rotator logic ultimately reduced the overall design complexity and prevented issues during simulation and synthesis.

Overall, this project allowed me to apply digital design concepts throughout the complete development process, from defining the architecture to simulation, synthesis, and final validation of the processor.